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  1. 学会・会議発表論文
  2. 学会・会議発表論文

Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling

http://hdl.handle.net/10228/5678
http://hdl.handle.net/10228/5678
001d1e50-55d0-49ed-a5ff-8b7e82b11a6a
名前 / ファイル ライセンス アクション
110828ats2011.pdf 110828ats2011.pdf (118.2 kB)
アイテムタイプ 会議発表論文 = Conference Paper(1)
公開日 2016-05-19
資源タイプ
資源タイプ識別子 http://purl.org/coar/resource_type/c_5794
資源タイプ conference paper
タイトル
タイトル Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling
言語 en
言語
言語 eng
著者 宮瀬, 紘平

× 宮瀬, 紘平

WEKO 6567
e-Rad 30452824
Scopus著者ID 6507979281
九工大研究者情報 219

en Miyase, Kohei

ja 宮瀬, 紘平

ja-Kana ミヤセ, コウヘイ

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Uchinodan, Y.

× Uchinodan, Y.

WEKO 16073

en Uchinodan, Y.

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Enokimoto, K.

× Enokimoto, K.

WEKO 16074

en Enokimoto, K.

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Yamato, Y.

× Yamato, Y.

WEKO 16075

en Yamato, Y.

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温, 暁青

× 温, 暁青

WEKO 1143
e-Rad 20250897
Scopus著者ID 7201738030
九工大研究者情報 300

en Wen, Xiaoqing

ja 温, 暁青


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梶原, 誠司

× 梶原, 誠司

WEKO 1147
e-Rad 80252592
Scopus著者ID 7005061314

ja 梶原, 誠司


en Kajihara, Seiji

ja-Kana カジハラ, セイジ

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Wu, F.

× Wu, F.

WEKO 16078

en Wu, F.

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Dilillo, L.

× Dilillo, L.

WEKO 16079

en Dilillo, L.

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Bosio, A.

× Bosio, A.

WEKO 16080

en Bosio, A.

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Girard, P.

× Girard, P.

WEKO 16081

en Girard, P.

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Virazel, A.

× Virazel, A.

WEKO 16082

en Virazel, A.

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抄録
内容記述タイプ Abstract
内容記述 It has become necessary to reduce power during LSI testing. Particularly, during at-speed testing, excessive power consumed during the Launch-To-Capture (LTC) cycle causes serious issues that may lead to the overkill of defect-free logic ICs. Many successful test generation approaches to reduce IR-drop and/or power supply noise during LTC for the launch-off capture (LOC) scheme have previously been proposed, and several of X-filling techniques have proven especially effective. With X-filling in the launch-off shift (LOS) scheme, however, adjacent-fill (which was originally proposed for shift-in power reduction) is used frequently. In this work, we propose a novel X-filling technique for the LOS scheme, called Adjacent-Probability-based X-Filling (AP-fill), which can reduce more LTC power than adjacent-fill. We incorporate AP-fill into a post-ATPG test modification flow consisting of test relaxation and X-filling in order to avoid the fault coverage loss and the test vector count inflation. Experimental results for larger ITC'99 circuits show that the proposed AP-fill technique can achieve a higher power reduction ratio than 0-fill, 1-fill, and adjacent-fill.
言語 en
備考
内容記述タイプ Other
内容記述 2011 Asian Test Symposium, 20-23 November 2011, New Delhi, India
書誌情報 en : 20th Asian test symposium : (ATS 2011) : New Delhi, India : 20-23 November 2011

巻 2011, p. 90-95, 発行日 2011-11-20
出版社
出版社 IEEE
DOI
関連タイプ isVersionOf
識別子タイプ DOI
関連識別子 https://doi.org/10.1109/ATS.2011.35
ISBN
識別子タイプ ISBN
関連識別子 978-1-4577-1984-4
ISSN
収録物識別子タイプ EISSN
収録物識別子 2377-5386
ISSN
収録物識別子タイプ PISSN
収録物識別子 1081-7735
著作権関連情報
権利情報 Copyright (c) 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
出版タイプ
出版タイプ AM
出版タイプResource http://purl.org/coar/version/c_ab4af688f83e57aa
査読の有無
値 yes
研究者情報
URL https://hyokadb02.jimu.kyutech.ac.jp/html/201_ja.html
連携ID
値 5410
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