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A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST
http://hdl.handle.net/10228/00006258
http://hdl.handle.net/10228/00006258d183126f-d09d-4831-844a-4a8cb742c46b
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
ats_203_208.pdf (353.7 kB)
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| アイテムタイプ | 会議発表論文 = Conference Paper(1) | |||||
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| 公開日 | 2017-07-11 | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||
| 資源タイプ | conference paper | |||||
| タイトル | ||||||
| タイトル | A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST | |||||
| 言語 | en | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| 著者 |
Kato, Takaaki
× Kato, Takaaki× Wang, Senling× Sato, Yasuo× 梶原, 誠司× 温, 暁青 |
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| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | High power dissipation during scan-based logic BIST is a crucial problem that leads to over-testing. Although controlling test power of a circuit under test (CUT) to an appropriate level is strongly required, it is not easy to control test power in BIST. This paper proposes a novel power controlling method to control the toggle rate of the patterns to an arbitrary level by modifying pseudo random patterns generated by a TPG (Test Pattern Generator) of logic BIST. While many approaches have been proposed to control the toggle rate of the patterns, the proposed approach can provide higher fault coverage. Experimental results show that the proposed approach can control toggle rates to a predetermined target level and modified patterns can achieve high fault coverage without increasing test time. | |||||
| 言語 | ja | |||||
| 備考 | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | 2016 IEEE 25th Asian Test Symposium (ATS), 21-24 Nov. 2016, Hiroshima, Japan | |||||
| 書誌情報 |
en : 2016 IEEE 25th Asian Test Symposium (ATS) p. 203-208, 発行日 2016-12-26 |
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| 出版社 | ||||||
| 出版社 | IEEE | |||||
| DOI | ||||||
| 関連タイプ | isVersionOf | |||||
| 識別子タイプ | DOI | |||||
| 関連識別子 | https://doi.org/10.1109/ATS.2016.59 | |||||
| ISSN | ||||||
| 収録物識別子タイプ | EISSN | |||||
| 収録物識別子 | 2377-5386 | |||||
| 著作権関連情報 | ||||||
| 権利情報 | Copyright (c) 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | scan shift power control | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | logic BIST | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | low power test | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | scan design | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | pseudo random pattern | |||||
| 出版タイプ | ||||||
| 出版タイプ | AM | |||||
| 出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||
| 査読の有無 | ||||||
| 値 | yes | |||||
| 研究者情報 | ||||||
| URL | https://hyokadb02.jimu.kyutech.ac.jp/html/201_ja.html | |||||
| 論文ID（連携） | ||||||
| 値 | 10303996 | |||||
| 連携ID | ||||||
| 値 | 6197 | |||||
