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On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST
http://hdl.handle.net/10228/00007517
http://hdl.handle.net/10228/00007517ae5efb78-26cb-483b-9c29-fe8d0a0cee20
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
ATS.2018.00017.pdf (432.3 kB)
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| アイテムタイプ | 会議発表論文 = Conference Paper(1) | |||||
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| 公開日 | 2020-01-09 | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||
| 資源タイプ | conference paper | |||||
| タイトル | ||||||
| タイトル | On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST | |||||
| 言語 | en | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| 著者 |
Oshima, Shigeyuki
× Oshima, Shigeyuki× Kato, Takaaki× Wang, Senling× Sato, Yasuo× 梶原, 誠司 |
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| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | Multi-cycle test with partial observation for scan-based logic BIST is known as one of effective methods to improve fault coverage without increase of test time. In the method, the selection of flip-flops for partial observation is critical to achieve high fault coverage with small area overhead. This paper proposes a selection method under the limitation to a number of flip-flops. The method consists of structural analysis of CUT and logic simulation of test vectors, therefore, it provides an easy implementation and a good scalability. Experimental results on benchmark circuits show that the method obtains higher fault coverage with less area overhead than the original method. Also the relation between the number of selected flip-flops and fault coverage is investigated. | |||||
| 言語 | en | |||||
| 備考 | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | 27th IEEE ASIAN TEST SYMPOSIUM (ATS'18), 15-18 October 2018, Hefei, China | |||||
| 書誌情報 |
en : 2018 IEEE 27th Asian Test Symposium (ATS) 発行日 2018-12-10 |
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| 出版社 | ||||||
| 出版社 | IEEE | |||||
| DOI | ||||||
| 関連タイプ | isVersionOf | |||||
| 識別子タイプ | DOI | |||||
| 関連識別子 | https://doi.org/10.1109/ATS.2018.00017 | |||||
| ISBN | ||||||
| 識別子タイプ | ISBN | |||||
| 関連識別子 | 978-1-5386-9466-4 | |||||
| ISBN | ||||||
| 識別子タイプ | ISBN | |||||
| 関連識別子 | 978-1-5386-9467-1 | |||||
| ISSN | ||||||
| 収録物識別子タイプ | EISSN | |||||
| 収録物識別子 | 2377-5386 | |||||
| ISSN | ||||||
| 収録物識別子タイプ | PISSN | |||||
| 収録物識別子 | 1081-7735 | |||||
| 著作権関連情報 | ||||||
| 権利情報 | Copyright (c) 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | logic BIST | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | scan test | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | multi-cycle test | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | partial observation | |||||
| 出版タイプ | ||||||
| 出版タイプ | AM | |||||
| 出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||
| 査読の有無 | ||||||
| 値 | yes | |||||
| 研究者情報 | ||||||
| URL | https://hyokadb02.jimu.kyutech.ac.jp/html/201_ja.html | |||||
| 論文ID（連携） | ||||||
| 値 | 10345121 | |||||
| 連携ID | ||||||
| 値 | 8027 | |||||
