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Physical design guides for substrate noise reduction in CMOSdigital circuits
http://hdl.handle.net/10228/994
http://hdl.handle.net/10228/99492e87a95-8132-4d2e-923e-75978cc63647
| 名前 / ファイル | ライセンス | アクション |
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Physical_20080221102129_001.pdf (4.4 MB)
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| アイテムタイプ | 学術雑誌論文 = Journal Article(1) | |||||||||||||
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| 公開日 | 2008-02-21 | |||||||||||||
| 資源タイプ | ||||||||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||||||||
| 資源タイプ | journal article | |||||||||||||
| タイトル | ||||||||||||||
| タイトル | Physical design guides for substrate noise reduction in CMOSdigital circuits | |||||||||||||
| 言語 | en | |||||||||||||
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| 言語 | eng | |||||||||||||
| 著者 |
Nagata, M
× Nagata, M× Nagai, J× Hijikata, K× 森江, 隆
WEKO
1615
× Iwata, A |
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| 抄録 | ||||||||||||||
| 内容記述タイプ | Abstract | |||||||||||||
| 内容記述 | Substrate noise injection in large-scale CMOS logic integrated circuits is quantitatively evaluated by 100-μV 100-ps resolution substrate noise measurements of controlled substrate noises by a transition-controllable noise source and practical substrate noises under CMOS logic operations. The noise injection is dominated by leaks of supply/return bounce into the substrate, and the noise intensity is determined by logic transition activity, according to experimental observations. A time-series divided parasitic capacitance model is derived as an efficient estimator of the supply current for simulating the substrate noise injection and can reproduce the measured substrate noise waveforms. The efficacy of physical noise reduction techniques at the layout and circuit levels is quantified and limitations are discussed in conjunction with the noise injection mechanisms. The reduced supply bounce CMOS circuit is proposed as a universal noise reduction technique, and more than 90% noise reduction to conventional CMOS is demonstrated | |||||||||||||
| 言語 | en | |||||||||||||
| 書誌情報 |
en : IEEE Journal of Solid-State Circuits 巻 36, 号 3, p. 539-549, 発行日 2001-03 |
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| 出版者 | IEEE | |||||||||||||
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| 関連タイプ | isIdenticalTo | |||||||||||||
| 識別子タイプ | DOI | |||||||||||||
| 関連識別子 | https://doi.org/10.1109/4.910494 | |||||||||||||
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| 関連タイプ | isIdenticalTo | |||||||||||||
| 識別子タイプ | URI | |||||||||||||
| 関連識別子 | https://cir.nii.ac.jp/crid/1050564288863194368 | |||||||||||||
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| 主題Scheme | NDC | |||||||||||||
| 主題 | 541 | |||||||||||||
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| 収録物識別子タイプ | NCID | |||||||||||||
| 収録物識別子 | AA00667434 | |||||||||||||
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| 収録物識別子タイプ | EISSN | |||||||||||||
| 収録物識別子 | 1558-173X | |||||||||||||
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| 収録物識別子タイプ | PISSN | |||||||||||||
| 収録物識別子 | 0018-9200 | |||||||||||||
| 著作権関連情報 | ||||||||||||||
| 権利情報 | ©2001 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | |||||||||||||
| 出版タイプ | ||||||||||||||
| 出版タイプ | VoR | |||||||||||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||||||||||
| 査読の有無 | ||||||||||||||
| 値 | yes | |||||||||||||
