WEKO3
アイテム
{"_buckets": {"deposit": "102f7c9f-8c56-4d5a-a1cb-371da91ecf07"}, "_deposit": {"created_by": 3, "id": "6395", "owners": [3], "pid": {"revision_id": 0, "type": "depid", "value": "6395"}, "status": "published"}, "_oai": {"id": "oai:kyutech.repo.nii.ac.jp:00006395", "sets": ["24"]}, "author_link": ["26774", "26771", "26770", "26776", "26775", "26773", "26769", "1143", "26777"], "item_21_biblio_info_6": {"attribute_name": "書誌情報", "attribute_value_mlt": [{"bibliographicIssueDates": {"bibliographicIssueDate": "2005-03-21", "bibliographicIssueDateType": "Issued"}, "bibliographic_titles": [{"bibliographic_title": "Design, Automation and Test in Europe"}]}]}, "item_21_description_4": {"attribute_name": "抄録", "attribute_value_mlt": [{"subitem_description": "This paper describes a flexible logic BIST scheme that features high fault coverage achieved by fault-simulation guided test point insertion, real at-speed test capability for multi-clock designs without clock frequency manipulation, and easy physical implementation due to the use of a low-speed SE signal. Application results of this scheme to two widely used IP cores are also reported.", "subitem_description_type": "Abstract"}]}, "item_21_description_5": {"attribute_name": "内容記述", "attribute_value_mlt": [{"subitem_description": "Design, Automation and Test in Europe (DATE05), 7-11 March 2005, Munich, Germany", "subitem_description_type": "Other"}]}, "item_21_description_60": {"attribute_name": "資源タイプ", "attribute_value_mlt": [{"subitem_description": "Journal Article", "subitem_description_type": "Other"}]}, "item_21_link_62": {"attribute_name": "研究者情報", "attribute_value_mlt": [{"subitem_link_text": "https://hyokadb02.jimu.kyutech.ac.jp/html/300_ja.html", "subitem_link_url": "https://hyokadb02.jimu.kyutech.ac.jp/html/300_ja.html"}]}, "item_21_publisher_7": {"attribute_name": "出版者", "attribute_value_mlt": [{"subitem_publisher": "IEEE"}]}, "item_21_relation_12": {"attribute_name": "DOI", "attribute_value_mlt": [{"subitem_relation_type": "isVersionOf", "subitem_relation_type_id": {"subitem_relation_type_id_text": "info:doi/10.1109/DATE.2005.70", "subitem_relation_type_select": "DOI"}}]}, "item_21_relation_14": {"attribute_name": "情報源", "attribute_value_mlt": [{"subitem_relation_name": [{"subitem_relation_name_text": "DOI: 10.1109/DATE.2005.70"}], "subitem_relation_type_id": {"subitem_relation_type_id_text": "DOI: 10.1109/DATE.2005.70", "subitem_relation_type_select": "URI"}}]}, "item_21_rights_13": {"attribute_name": "権利", "attribute_value_mlt": [{"subitem_rights": "Copyright (c) 2005 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works."}]}, "item_21_select_59": {"attribute_name": "査読の有無", "attribute_value_mlt": [{"subitem_select_item": "yes"}]}, "item_21_source_id_8": {"attribute_name": "ISSN", "attribute_value_mlt": [{"subitem_source_identifier": "1530-1591", "subitem_source_identifier_type": "ISSN"}, {"subitem_source_identifier": "1558-1101", "subitem_source_identifier_type": "ISSN"}]}, "item_21_subject_16": {"attribute_name": "日本十進分類法", "attribute_value_mlt": [{"subitem_subject": "548", "subitem_subject_scheme": "NDC"}]}, "item_21_text_28": {"attribute_name": "論文ID(連携)", "attribute_value_mlt": [{"subitem_text_value": "10056654"}]}, "item_21_text_36": {"attribute_name": "著者所属", "attribute_value_mlt": [{"subitem_text_value": "Samsung Electronics, Co."}, {"subitem_text_value": "Samsung Electronics, Co."}, {"subitem_text_value": "SynTest Technologies, Inc."}, {"subitem_text_value": "Kyushu Institute of Technology"}, {"subitem_text_value": "SynTest Technologies, Inc., Taiwan"}, {"subitem_text_value": "SynTest Korea, Ltd."}, {"subitem_text_value": "SynTest Korea, Ltd."}, {"subitem_text_value": "SynTest Technologies, Inc., Taiwan"}, {"subitem_text_value": "SynTest Technologies, Inc."}]}, "item_21_text_63": {"attribute_name": "連携ID", "attribute_value_mlt": [{"subitem_text_value": "8113"}]}, "item_21_version_type_58": {"attribute_name": "著者版フラグ", "attribute_value_mlt": [{"subitem_version_resource": "http://purl.org/coar/version/c_ab4af688f83e57aa", "subitem_version_type": "AM"}]}, "item_creator": {"attribute_name": "著者", "attribute_type": "creator", "attribute_value_mlt": [{"creatorNames": [{"creatorName": "Cheon, B."}], "nameIdentifiers": [{"nameIdentifier": "26769", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Lee, E."}], "nameIdentifiers": [{"nameIdentifier": "26770", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Wang, L.-T."}], "nameIdentifiers": [{"nameIdentifier": "26771", "nameIdentifierScheme": "WEKO"}]}, {"creatorAffiliations": [{"affiliationNameIdentifiers": [], "affiliationNames": [{"affiliationName": "", "affiliationNameLang": "ja"}]}], "creatorNames": [{"creatorName": "Wen, Xiaoqing", "creatorNameLang": "en"}, {"creatorName": "温, 暁青", "creatorNameLang": "ja"}, {"creatorName": "オン, ギョウセイ", "creatorNameLang": "ja-Kana"}], "familyNames": [{"familyName": "Wen", "familyNameLang": "en"}, {"familyName": "温", "familyNameLang": "ja"}, {"familyName": "オン", "familyNameLang": "ja-Kana"}], "givenNames": [{"givenName": "Xiaoqing", "givenNameLang": "en"}, {"givenName": "暁青", "givenNameLang": "ja"}, {"givenName": "ギョウセイ", "givenNameLang": "ja-Kana"}], "nameIdentifiers": [{"nameIdentifier": "1143", "nameIdentifierScheme": "WEKO"}, {"nameIdentifier": "20250897", "nameIdentifierScheme": "e-Rad", "nameIdentifierURI": "https://nrid.nii.ac.jp/ja/nrid/1000020250897"}, {"nameIdentifier": "7201738030", "nameIdentifierScheme": "Scopus著者ID", "nameIdentifierURI": "https://www.scopus.com/authid/detail.uri?authorId=7201738030"}, {"nameIdentifier": "300", "nameIdentifierScheme": "九工大研究者情報", "nameIdentifierURI": "https://hyokadb02.jimu.kyutech.ac.jp/html/300_ja.html"}]}, {"creatorNames": [{"creatorName": "Hsu, P."}], "nameIdentifiers": [{"nameIdentifier": "26773", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Cho, J."}], "nameIdentifiers": [{"nameIdentifier": "26774", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Park, J."}], "nameIdentifiers": [{"nameIdentifier": "26775", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Chao, H."}], "nameIdentifiers": [{"nameIdentifier": "26776", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Wu, S."}], "nameIdentifiers": [{"nameIdentifier": "26777", "nameIdentifierScheme": "WEKO"}]}]}, "item_files": {"attribute_name": "ファイル情報", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_date", "date": [{"dateType": "Available", "dateValue": "2020-02-06"}], "displaytype": "detail", "download_preview_message": "", "file_order": 0, "filename": "10056654.pdf", "filesize": [{"value": "54.1 kB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_free", "mimetype": "application/pdf", "size": 54100.0, "url": {"label": "10056654.pdf", "url": "https://kyutech.repo.nii.ac.jp/record/6395/files/10056654.pdf"}, "version_id": "aa6ee7d7-8115-4d90-9922-5c459b6c64fb"}]}, "item_keyword": {"attribute_name": "キーワード", "attribute_value_mlt": [{"subitem_subject": "Built-in self-test", "subitem_subject_scheme": "Other"}, {"subitem_subject": "Logic testing", "subitem_subject_scheme": "Other"}, {"subitem_subject": "Circuit testing", "subitem_subject_scheme": "Other"}, {"subitem_subject": "Clocks", "subitem_subject_scheme": "Other"}, {"subitem_subject": "Circuit faults", "subitem_subject_scheme": "Other"}, {"subitem_subject": "System testing", "subitem_subject_scheme": "Other"}, {"subitem_subject": "Frequency", "subitem_subject_scheme": "Other"}, {"subitem_subject": "Logic circuits", "subitem_subject_scheme": "Other"}, {"subitem_subject": "Logic design", "subitem_subject_scheme": "Other"}, {"subitem_subject": "Costs", "subitem_subject_scheme": "Other"}]}, "item_language": {"attribute_name": "言語", "attribute_value_mlt": [{"subitem_language": "eng"}]}, "item_resource_type": {"attribute_name": "資源タイプ", "attribute_value_mlt": [{"resourcetype": "journal article", "resourceuri": "http://purl.org/coar/resource_type/c_6501"}]}, "item_title": "At-Speed Logic BIST for IP Cores", "item_titles": {"attribute_name": "タイトル", "attribute_value_mlt": [{"subitem_title": "At-Speed Logic BIST for IP Cores"}]}, "item_type_id": "21", "owner": "3", "path": ["24"], "permalink_uri": "http://hdl.handle.net/10228/00007605", "pubdate": {"attribute_name": "公開日", "attribute_value": "2020-02-06"}, "publish_date": "2020-02-06", "publish_status": "0", "recid": "6395", "relation": {}, "relation_version_is_last": true, "title": ["At-Speed Logic BIST for IP Cores"], "weko_shared_id": 3}
At-Speed Logic BIST for IP Cores
http://hdl.handle.net/10228/00007605
http://hdl.handle.net/10228/00007605fdc557f7-5c37-4932-9026-02f27c856b8c
名前 / ファイル | ライセンス | アクション |
---|---|---|
10056654.pdf (54.1 kB)
|
|
Item type | 学術雑誌論文 = Journal Article(1) | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
公開日 | 2020-02-06 | |||||||||||
資源タイプ | ||||||||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||||||
資源タイプ | journal article | |||||||||||
タイトル | ||||||||||||
タイトル | At-Speed Logic BIST for IP Cores | |||||||||||
言語 | ||||||||||||
言語 | eng | |||||||||||
著者 |
Cheon, B.
× Cheon, B.× Lee, E.× Wang, L.-T.× 温, 暁青
WEKO
1143
× Hsu, P.× Cho, J.× Park, J.× Chao, H.× Wu, S. |
|||||||||||
抄録 | ||||||||||||
内容記述タイプ | Abstract | |||||||||||
内容記述 | This paper describes a flexible logic BIST scheme that features high fault coverage achieved by fault-simulation guided test point insertion, real at-speed test capability for multi-clock designs without clock frequency manipulation, and easy physical implementation due to the use of a low-speed SE signal. Application results of this scheme to two widely used IP cores are also reported. | |||||||||||
備考 | ||||||||||||
内容記述タイプ | Other | |||||||||||
内容記述 | Design, Automation and Test in Europe (DATE05), 7-11 March 2005, Munich, Germany | |||||||||||
書誌情報 |
Design, Automation and Test in Europe 発行日 2005-03-21 |
|||||||||||
出版社 | ||||||||||||
出版者 | IEEE | |||||||||||
DOI | ||||||||||||
関連タイプ | isVersionOf | |||||||||||
識別子タイプ | DOI | |||||||||||
関連識別子 | info:doi/10.1109/DATE.2005.70 | |||||||||||
日本十進分類法 | ||||||||||||
主題Scheme | NDC | |||||||||||
主題 | 548 | |||||||||||
ISSN | ||||||||||||
収録物識別子タイプ | ISSN | |||||||||||
収録物識別子 | 1530-1591 | |||||||||||
ISSN | ||||||||||||
収録物識別子タイプ | ISSN | |||||||||||
収録物識別子 | 1558-1101 | |||||||||||
著作権関連情報 | ||||||||||||
権利情報 | Copyright (c) 2005 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | Built-in self-test | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | Logic testing | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | Circuit testing | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | Clocks | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | Circuit faults | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | System testing | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | Frequency | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | Logic circuits | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | Logic design | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | Costs | |||||||||||
出版タイプ | ||||||||||||
出版タイプ | AM | |||||||||||
出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||||||||
査読の有無 | ||||||||||||
値 | yes | |||||||||||
研究者情報 | ||||||||||||
https://hyokadb02.jimu.kyutech.ac.jp/html/300_ja.html | ||||||||||||
論文ID(連携) | ||||||||||||
10056654 | ||||||||||||
連携ID | ||||||||||||
8113 | ||||||||||||
情報源 | ||||||||||||
識別子タイプ | URI | |||||||||||
関連識別子 | DOI: 10.1109/DATE.2005.70 | |||||||||||
関連名称 | DOI: 10.1109/DATE.2005.70 |