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On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST
http://hdl.handle.net/10228/00007595
http://hdl.handle.net/10228/0000759544604ed4-1ab8-482f-ab27-13d80490d8d9
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
10274078.pdf (770.2 kB)
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| アイテムタイプ | 学術雑誌論文 = Journal Article(1) | |||||
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| 公開日 | 2020-02-04 | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
| 資源タイプ | journal article | |||||
| タイトル | ||||||
| タイトル | On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST | |||||
| 言語 | en | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| 著者 |
Tomita, A.
× Tomita, A.× 温, 暁青× Sato, Y.× 梶原, 誠司× Girard, P.× Tehranipoor, M.× Wang, L.-T. |
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| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | The applicability of at-speed scan-based logic built-in self-test (BIST) is being severely challenged by excessive capture power that may cause erroneous test responses for good chips. Different from conventional low-power BIST, this paper is the first that has explicitly focused on achieving capture power safety with a practical scheme called capture-power-safe BIST (CPS-BIST). The basic idea is to identify all possibly erroneous test responses and use the well-known technique of mask (partial-mask or full-mask) to block them from reaching the MISR. Experiments with large benchmark and industrial circuits show that CPS-BIST can achieve capture power safety with negligible impact on both test quality and area overhead. | |||||
| 言語 | en | |||||
| 備考 | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | 2013 22nd Asian Test Symposium, 18-21 November 2013, Jiaosi Township, Taiwan | |||||
| 書誌情報 |
en : 2013 22nd Asian Test Symposium p. 19-24, 発行日 2013-12-23 |
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| 出版社 | ||||||
| 出版者 | IEEE | |||||
| DOI | ||||||
| 関連タイプ | isVersionOf | |||||
| 識別子タイプ | DOI | |||||
| 関連識別子 | https://doi.org/10.1109/ATS.2013.14 | |||||
| 日本十進分類法 | ||||||
| 主題Scheme | NDC | |||||
| 主題 | 548 | |||||
| ISSN | ||||||
| 収録物識別子タイプ | PISSN | |||||
| 収録物識別子 | 1081-7735 | |||||
| ISSN | ||||||
| 収録物識別子タイプ | EISSN | |||||
| 収録物識別子 | 2377-5386 | |||||
| 著作権関連情報 | ||||||
| 権利情報 | Copyright (c) 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Built-in self-test | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Safety | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Vectors | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Radiation detectors | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Logic gates | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Switches | |||||
| 出版タイプ | ||||||
| 出版タイプ | AM | |||||
| 出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||
| 査読の有無 | ||||||
| 値 | yes | |||||
| 研究者情報 | ||||||
| URL | https://hyokadb02.jimu.kyutech.ac.jp/html/300_ja.html | |||||
| 論文ID（連携） | ||||||
| 値 | 10274078 | |||||
| 連携ID | ||||||
| 値 | 8105 | |||||
