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Power-Aware Testing For Low-Power VLSI Circuits
http://hdl.handle.net/10228/00007624
http://hdl.handle.net/10228/00007624b24d5512-2fd5-4640-bbec-e61d8cfb21f7
| 名前 / ファイル | ライセンス | アクション |
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10317319.pdf (833.3 kB)
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| アイテムタイプ | 学術雑誌論文 = Journal Article(1) | |||||
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| 公開日 | 2020-02-19 | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
| 資源タイプ | journal article | |||||
| タイトル | ||||||
| タイトル | Power-Aware Testing For Low-Power VLSI Circuits | |||||
| 言語 | en | |||||
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| 言語 | eng | |||||
| 著者 |
温, 暁青
× 温, 暁青 |
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| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | Low-power VLSI circuits are indispensable for almost all types of modern electronic devices, from battery-driven mobile gadgets to harvested-energy-driven wireless sensor systems. However, the testing of such low-power VLSI circuits has become a big challenge, especially due to the excessive power dissipation during scan testing. This paper will highlight three major test-power-induced problems (namely heat, false failures, clock stretch) and describe how to mitigate them with power-aware VLSI testing. Future research topics in this field will also be discussed. | |||||
| 言語 | en | |||||
| 備考 | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT-2016), 25-28 October 2016, Hangzhou, China | |||||
| 言語 | en | |||||
| 書誌情報 |
en : 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) p. 585-588, 発行日 2017-08-03 |
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| 出版社 | ||||||
| 出版者 | IEEE | |||||
| DOI | ||||||
| 関連タイプ | isVersionOf | |||||
| 識別子タイプ | DOI | |||||
| 関連識別子 | https://doi.org/10.1109/ICSICT.2016.7998986 | |||||
| ISBN | ||||||
| 識別子タイプ | ISBN | |||||
| 関連識別子 | 978-1-4673-9717-9 | |||||
| ISBN | ||||||
| 識別子タイプ | ISBN | |||||
| 関連識別子 | 978-1-4673-9719-3 | |||||
| 日本十進分類法 | ||||||
| 主題Scheme | NDC | |||||
| 主題 | 548 | |||||
| 著作権関連情報 | ||||||
| 権利情報 | Copyright (c) 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Clocks | |||||
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| 主題Scheme | Other | |||||
| 主題 | Switches | |||||
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| 主題Scheme | Other | |||||
| 主題 | Testing | |||||
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| 主題Scheme | Other | |||||
| 主題 | Very large scale integration | |||||
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| 主題Scheme | Other | |||||
| 主題 | Logic gates | |||||
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| 主題Scheme | Other | |||||
| 主題 | Lead | |||||
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| 主題Scheme | Other | |||||
| 主題 | Flip-flops | |||||
| 出版タイプ | ||||||
| 出版タイプ | AM | |||||
| 出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||
| 査読の有無 | ||||||
| 値 | yes | |||||
| 研究者情報 | ||||||
| URL | https://hyokadb02.jimu.kyutech.ac.jp/html/300_ja.html | |||||
| 論文ID（連携） | ||||||
| 値 | 10317319 | |||||
| 連携ID | ||||||
| 値 | 8130 | |||||
