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  1. 学術雑誌論文
  2. 5 技術(工学)

Path Delay Measurement with Correction for Temperature And Voltage Variations

http://hdl.handle.net/10228/00008155
http://hdl.handle.net/10228/00008155
a2d8b1b3-fcc7-45ba-b78a-4e04cd414925
名前 / ファイル ライセンス アクション
10362957.pdf 10362957.pdf (2.1 MB)
アイテムタイプ 学術雑誌論文 = Journal Article(1)
公開日 2021-04-08
資源タイプ
資源タイプ識別子 http://purl.org/coar/resource_type/c_6501
資源タイプ journal article
タイトル
タイトル Path Delay Measurement with Correction for Temperature And Voltage Variations
言語 en
言語
言語 eng
著者 Miyake, Yousuke

× Miyake, Yousuke

WEKO 29874

en Miyake, Yousuke
Miyake, Y.

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Kato, Takaaki

× Kato, Takaaki

WEKO 29875

en Kato, Takaaki
Kato, T.

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梶原, 誠司

× 梶原, 誠司

WEKO 1147
e-Rad 80252592
Scopus著者ID 7005061314

ja 梶原, 誠司

en Kajihara, Seiji

ja-Kana カジハラ, セイジ


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抄録
内容記述タイプ Abstract
内容記述 Path delay measurement in field is useful for not only detection of delay-related faults but also prediction of aging-induced delay faults. In order to utilize the delay measurement results for fault detection and fault prediction, the measured delay must be corrected because the circuit delay is varied in field due to environment such as temperature or voltage variations. This paper proposes a method of BIST-based path delay measurement in which the influence of environmental variations is eliminated. An on-chip sensor measures temperature and voltage during delay measurement. Using information from the temperature and voltage sensor and pre-computed temperature and voltage sensitivities of the circuit delay, the measured delay value is corrected to a delay value that would be obtained under a fixed temperature and voltage. Evaluation for a test chip with 65nm CMOS technology implementing the proposed method shows that errors of measured delays brought by environmental variations could be reduced from 2419 to 211 ps in the range of 30 to 80 °C and 1.05 to 1.35 V. This paper also discusses application and feasibility for degradation detection of the proposed method.
言語 en
備考
内容記述タイプ Other
内容記述 International Test Conference in Asia (ITC-Asia 2020), September 23-25, 2020, Taipei City, Taiwan(現地およびオンラインで開催)
書誌情報 en : 2020 IEEE International Test Conference in Asia (ITC-Asia)

p. 112-117, 発行日 2020-10-16
出版社
出版者 IEEE
DOI
関連タイプ isVersionOf
識別子タイプ DOI
関連識別子 https://doi.org/10.1109/ITC-Asia51099.2020.00031
ISBN
識別子タイプ ISBN
関連識別子 978-1-7281-8944-4
ISBN
識別子タイプ ISBN
関連識別子 978-1-7281-8945-1
日本十進分類法
主題Scheme NDC
主題 549
著作権関連情報
権利情報 Copyright (c) 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
キーワード
主題Scheme Other
主題 Field test
キーワード
主題Scheme Other
主題 Logic BIST
キーワード
主題Scheme Other
主題 Delay measurement
キーワード
主題Scheme Other
主題 Degradation detection
キーワード
主題Scheme Other
主題 Temperature and voltage variation
出版タイプ
出版タイプ AM
出版タイプResource http://purl.org/coar/version/c_ab4af688f83e57aa
査読の有無
値 yes
研究者情報
URL https://hyokadb02.jimu.kyutech.ac.jp/html/201_ja.html
論文ID(連携)
値 10362957
連携ID
値 8667
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