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マルチフォールトモデルを対象としたLSIのテストに関する研究
http://hdl.handle.net/10228/564
http://hdl.handle.net/10228/564a6f5cf84-91d4-4379-920b-e17101f5a4b1
Item type | 研究報告書 = Research Paper(1) | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
公開日 | 2007-12-25 | |||||||||||
資源タイプ | ||||||||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_18ws | |||||||||||
資源タイプ | research report | |||||||||||
タイトル | ||||||||||||
タイトル | マルチフォールトモデルを対象としたLSIのテストに関する研究 | |||||||||||
言語 | ||||||||||||
言語 | jpn | |||||||||||
著者 |
梶原, 誠司
× 梶原, 誠司
WEKO
1147
|
|||||||||||
備考 | ||||||||||||
内容記述タイプ | Other | |||||||||||
内容記述 | 平成16年度-平成18年度科学研究費補助金(基盤研究(C))研究成果報告書 | |||||||||||
書誌情報 | 発行日 2007-03 | |||||||||||
出版社 | ||||||||||||
出版者 | 九州工業大学 | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | design and test of LSIS | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | Logic circuit | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | fault diagrosis | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | test pattern generation | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | dependability | |||||||||||
査読の有無 | ||||||||||||
値 | no | |||||||||||
科研課題番号 | ||||||||||||
16500036 | ||||||||||||
著者所属 | ||||||||||||
九州工業大学情報工学部 | ||||||||||||
備考 | ||||||||||||
別刷論文(p19-25,36-43,52-69)削除 / 登録別刷論文(1)Scan Tree Design: Test Compression with Test Vector Modification, IPSJ journal, vol.44, No.5, pp.1270-1278, 2004, copyright(社)情報処理学会 / 登録別刷論文(2)多重スキャンツリー設計によるテストデータ量・テスト印加時間の削減, 情報処理学会論文誌, vol.47, No.6, pp.1648-1657, 2006, copyright(社)情報処理学会 / 登録別刷論文(3)Hybrid fault simulation with compiled and event-driven methods, Proc. IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, pp.240-243, 2006, ©2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE / 登録別刷論文(4)A Framework of High-quality Transition Fault ATPG for Scan Circuits, Proc. International Test Conference, paper 2.1, 2006, ©2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE |