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VirtualScan: a new compressed scan technology for test cost reduction
http://hdl.handle.net/10228/00007604
http://hdl.handle.net/10228/00007604618acf24-6b00-4d4f-8ee0-a34d79d891a4
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
10056652.pdf (176.9 kB)
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| アイテムタイプ | 学術雑誌論文 = Journal Article(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2020-02-06 | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
| 資源タイプ | journal article | |||||
| タイトル | ||||||
| タイトル | VirtualScan: a new compressed scan technology for test cost reduction | |||||
| 言語 | en | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| 著者 |
Wang, Laung-Terng
× Wang, Laung-Terng× 温, 暁青× Furukawa, Hiroshi× Hsu, Fei-Sheng× Lin, Shyh-Horng× Tsai, Sen-Wei× Abdel-Hafez, Khader S.× Wu, Shianling |
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| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | This work describes the VirtualScan technology for scan test cost reduction. Scan chains in a VirtualScan circuit are split into shorter ones and the gap between external scan ports and internal scan chains are bridged with a broadcaster and a compactor. Test patterns for a VirtualScan circuit are generated directly by one-pass VirtualScan ATPG, in which multi-capture clocking and maximum test compaction are supported. In addition, VirtualScan ATPG avoids unknown-value and aliasing effects algorithmically without adding any additional circuitry. The VirtualScan technology has achieved successful tape-outs of industrial chips and has been proven to be an efficient and easy-to-implement solution for scan test cost reduction. | |||||
| 言語 | en | |||||
| 備考 | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | 2004 International Conference on Test, 26-28 October 2004, Charlotte, NC, USA, USA | |||||
| 書誌情報 |
en : 2004 International Conference on Test 発行日 2005-01-31 |
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| 出版社 | ||||||
| 出版者 | IEEE | |||||
| DOI | ||||||
| 関連タイプ | isVersionOf | |||||
| 識別子タイプ | DOI | |||||
| 関連識別子 | https://doi.org/10.1109/TEST.2004.1387356 | |||||
| ISBN | ||||||
| 識別子タイプ | ISBN | |||||
| 関連識別子 | 0-7803-8580-2 | |||||
| 日本十進分類法 | ||||||
| 主題Scheme | NDC | |||||
| 主題 | 548 | |||||
| 著作権関連情報 | ||||||
| 権利情報 | Copyright (c) 2004 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Costs | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Circuit testing | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Integrated circuit testing | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Circuit faults | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Automatic test pattern generation | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Electronic equipment testing | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Automatic testing | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | System testing | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Manufacturing | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Built-in self-test | |||||
| 出版タイプ | ||||||
| 出版タイプ | AM | |||||
| 出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||
| 査読の有無 | ||||||
| 値 | yes | |||||
| 研究者情報 | ||||||
| URL | https://hyokadb02.jimu.kyutech.ac.jp/html/300_ja.html | |||||
| 論文ID（連携） | ||||||
| 値 | 10056652 | |||||
| 連携ID | ||||||
| 値 | 8112 | |||||
